Image capturing device

ABSTRACT

An image capturing device having a function of clamping an image signal. When the image capturing device is activated, a synchronous signal generating section begins creation of a horizontal synchronous signal, and a counter begins counting a pulse of the horizontal synchronous signal. When the counted value reaches a predetermined value, the clamping capability control section changes the level of a clamp mode signal to an H level. During a period from the start of power supply to the image capturing device to the raising of the level of a clamp mode signal to an H level, a clamp pulse generating section sets a longer width for a clamp pulse than in a normal operation so that a switch element of a clamping circuit remains in an on state in a longer period, whereby a smaller time constant for clamping is set. After elapse of a predetermined period, the switch element is controlled so as to remain in an ON state in a normal period, which is relatively short, whereby a larger time constant for clamping is set. With this arrangement, noise which would be caused with a small clamping time constant is suppressed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image capturing device forgenerating an image signal to output using an image capturing elementand, in particular, to clamping of an image signal.

2. Description of the Related Art

An image signal captured by an image capturing element such as a CCD(charge coupled device) image sensor or the like is generally coupled bya capacitor for extraction. Therefore, the DC level of an image signalcan fluctuate depending on the level of an image. In order to addressthis problem, an image signal corresponding to an optical black (OPB)region which is provided at the periphery of the pixel alignment ofimage capturing elements is clamped at a predetermined black level. Inclamping, a signal terminal which outputs an image signal coupled by thecapacitor is connected to a reference power source during an OPB imagesignal period.

An OPB region is provided surrounding the effective image capturingregion, as described above. That is, a small number of top and bottompixel lines of a plurality of horizontal lines which constitute theimage alignment of image capturing elements, and a small number ofpixels respectively at the leading and trailing ends of the horizontallines constitute an OPB region. Clamping is applied during an OPB imagesignal period for each horizontal line, therefore periodically, and theperiodical clamping for every horizontal line can suppress fluctuationof the DC level of an image signal which would otherwise be causedduring a vertical scanning period.

FIG. 11 schematically shows a circuit structure of a conventional imagecapturing device, which comprises a CCD image sensor 2, a clampingcircuit 4, an analogue signal processing circuit 6, an A/D(analogue/digital) converter 8, and a digital signal processing circuit10. An image signal generated by the CCD image sensor 2 is coupled by acapacitor 4 a in the clamping circuit 4 to be extracted to a signal line22. The extracted image signal is subjected to predetermined signalprocessing in the analogue signal processing circuit 6, the A/Dconverter 8, and the digital signal processing circuit 10 before beingoutput to, for example, a display device, or the like.

The clamping circuit 4 is a circuit for clamping the potential of thesignal line 22, and comprises a buffer circuit 4 b, which serves as areference voltage source, and a switch element 4 c for connecting thebuffer circuit 4 b and the signal line 22. The buffer circuit 4 bcomprises, for example, two transistors M1, M2 serially connectedbetween the power source terminal and the ground terminal and outputs avoltage between the two transistors M1 and M2 as a reference voltage.The transistor M1 receives via its gate a first control voltage V1,according to which a current flowing in the buffer circuit 4 b isdetermined. The transistor M2 receives via its gate a second controlvoltage V2, according to which an output voltage of the buffer circuit 4b is determined. The opening and closing of the switch element 4 c iscontrolled in response to a clamp pulse CP, which is generated by atiming control circuit, not shown.

FIG. 12 is a timing chart explaining operation of a conventionalclamping circuit. Specifically, a clamp pulse 30 is caused insynchronism with a horizontal synchronous signal HT. Each clamp pulse 30has a predetermined width, during a period corresponding to which theswitch element 4 c remains in an ON state so that an output voltageV_(K) of the buffer circuit 4 b is applied to the signal line 22. Aclamp pulse 30 is caused within an OPB image signal period at thebeginning of each horizontal line, so that an OPB image signal isclamped at a predetermined potential whereby a black level is fixed at aconstant level.

In clamping, a current is supplied from the buffer circuit 4 b to thesignal line 22, so that the potential of the signal line 22 is madecloser to an output voltage V_(K) of the buffer circuit 4 b. The size ofthe potential change in the signal line 22 caused in a singleapplication of clamping is here referred to as the “clamping capability.Clamping capability depends on current supply capacity of the buffercircuit 4 b and a period of time in which the switch element 4 c remainsin an ON state. That is, the larger the current supply capacity of thebuffer circuit 4 b or the longer the electric conductive time, thelarger the ensured clamping capability.

Here, the more the clamping capability is enhanced, the more a DC levelto be set becomes likely to follow noise in an OPB image signal period.Consequently, a DC level of an image signal fluctuates for everyhorizontal line, causing combing noise in a reproduced image.

In order to address this problem, clamping capability is set at such arelatively low level, rather than the maximum level, that a relativelylarge number of lines are clamped at a predetermined level so that noiseinfluence can be leveled and combing noise can be suppressed. Forexample, conventionally, clamping capability is set at such a timeconstant that achieves potential conversion which converts, while takingthe whole file period, the potential at an output terminal into apotential at a predetermined level.

While image capturing does not take place, an image capturing element isnot driven so that power consumption in the image capturing element, thedriving circuit, and the signal processing circuit can be suppressed.During such a period, no OPB image signal is obtained and clamping isnot applied, and, therefore, the potential at the output terminal iscaused to change due to discharge from the capacitor while the imagecapturing element is not driven.

As described above, conventionally, a suppressed clamping capability,rather than the maximum clamping capability, is employed to preventcombing noise. Therefore, there exists a problem that a longer period oftime is required, at the time of start of driving of an image capturingelement, before the potential at the output terminal becomes stabilizedwith the image capturing element operating in a stable state. In turn, alonger period of time is required before an image settles in a stablestate.

This process necessary to increase a clamping level to a predeterminedpotential level is one of the factors which hinders time reduction inactivation of an image capturing device.

SUMMARY OF THE INVENTION

The present invention provides an image capturing device capable ofprompt clamping of the potential at an output terminal at apredetermined level at the time driving of an image capturing element isbegun, so that a normal image can be promptly obtained.

An image capturing device of the present invention comprises a solidimage capturing element; a driving circuit for driving the solid imagecapturing element to obtain an image signal; a clamping circuit forclamping a reference level of the image signal generated by the solidimage capturing element at a predetermined level; and a control circuitfor controlling clamping capability of the clamping circuit. Theclamping circuit gradually clamps the reference level of an image signalat a predetermined potential level.

In the present invention, clamping capability, which indicates an amountof a potential change caused by a single application of clamping, is setat a relatively low level during a period in which the solid imagecapturing element operates in a stable stage after a transitional periodfollowing the activation. Specifically, the clamping capability at thattime may be set, for example, at such a level that enables reduction ofcombing noise to below an acceptable level.

Meanwhile, during a predetermined activation period after start ofdriving the solid image capturing element, the clamping capability isset at a different level from the above, in particular, to a higherlevel. Because the clamping capability is at a higher level, an imagecan promptly settle in a stable state with a stable DC level. The higherlevel of the clamping capability which is set during the predeterminedactivation period after the start of driving may be constant or changethroughout the period.

In the present invention, the clamping circuit may further comprise abuffer circuit for outputting a predetermined reference voltage; and aswitch connected between the buffer circuit and a signal line connectedto an output terminal of the sold image capturing element, for switchingbetween in an on state and in an off state. The control circuit controlsclamping capability by changing a period of time in which the switchremains in an ON state.

In the present invention, the clamping circuit may also comprise aplurality of buffer circuits for each outputting a predeterminedreference voltage; and a selector for selecting at least one of theplurality of buffer circuits; a switch connected between the buffercircuit selected by the selector and a signal line connected to anoutput terminal of the sold image capturing element, for switchingbetween in an on state and in an off state. The control circuit controlsclamping capability by changing selection by the selector.

Still further in the present invention, a clamping capability attainedin a predetermined period of time after activation of image capturingmay be controlled according to a preceding period of time in which imagecapturing by the solid image capturing element remains suspended, or aninoperative period. In general, the longer the inoperative period, thelarger a potential difference in a signal line between when the solidimage capturing element is operating and when it is not is caused.Therefore, a higher level of clamping capability is set for a longerinoperative period, so that an image with a stable DC level can bepromptly obtained.

The present invention will be clearly understood from the description onthe embodiments below. It should, however, be noted that the embodimentsdescribed below are only for illustration, and do not limit the scope ofthe present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a circuit structure of an image capturingdevice;

FIG. 2A is a timing chart concerning a power source;

FIG. 2B is a timing chart concerning an internal system clock;

FIG. 2C is a timing chart concerning a horizontal synchronous signal;

FIG. 2D is a timing chart concerning a clamp mode signal;

FIG. 3A is a timing chart for a horizontal synchronous signal;

FIG. 3B is a timing chart for a clamp pulse;

FIG. 3C is a timing chart for a clamp mode signal;

FIG. 4 is a graph showing a relationship between the time after start ofpower supply and the additional amount of a pulse width;

FIG. 5 is a graph showing relationship between an inoperative period andan additional amount of a pulse width;

FIG. 6 is a graph showing a relationship between the time after start ofpower supply and the additional amount of a pulse width, using aninoperative period as a parameter;

FIG. 7A is a timing chart concerning a power source;

FIG. 7B is a timing chart concerning a stand-by signal;

FIG. 7C is a timing chart concerning an internal system clock;

FIG. 7D is a timing chart concerning a horizontal synchronous signal;

FIG. 7E is a timing chart concerning a clamp mode signal.

FIG. 8 is a diagram showing another structure of a clamping circuit;

FIG. 9 is a diagram explaining operation of the clamping circuit of FIG.8;

FIG. 10 is a diagram explaining operation of the clamping circuit ofFIG. 8;

FIG. 11 is a diagram showing a structure of a conventional imagecapturing device; and

FIG. 12 is a timing chart for a conventional clamping circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, embodiments of the present invention will be describedwith reference to the accompanied drawings.

FIG. 1 is a diagram schematically showing a circuit structure of anembodiment of the present invention. This device comprises a CCD imagesensor 50, a clamping circuit 52, an analogue signal processing circuit54, an A/D converter circuit 56, a digital signal processing circuit 58,a timing control circuit 60, a boosting circuit 62, a vertical driver64, a horizontal driver 66, and a regulate circuit 68.

This device is activated for image capturing either by supplying ofpower or awaking the device from a stand-by mode, being a mode in whichthe power source circuits such as the boosting circuit 62 and theregulate circuit 68 remain powered but inoperative. Because in astand-by mode, no operating voltage is supplied to CCD driver circuits,including the vertical driver 64 and the horizontal driver 66, powerconsumption can be suppressed.

A power voltage VD is supplied to the boosting circuit 62, which in turnboosts the supplied power voltage VD to generate a positively boostedvoltage VOH and a negatively boosted voltage VOL. The generated, boostedvoltages VOH and VOL are supplied to the CCD image sensor 50 and thevertical driver 64, respectively. A power voltage VD is also supplied tothe regulate circuit 68, which in turn depresses the supplied powervoltage VD to generate a predetermined regulating voltage VJ [Maybe“regulating voltage VJ” or “regulated voltage VJ”? Globally replace, ifnecessary.] to output. The output regulating voltage VJ is utilized inthe analogue signal processing circuit 54, the A/D converter circuit 56,the digital signal processing circuit 58, and the horizontal driver 66.

The CCD image sensor 50 may be, for example, a frame-transfer type andmay comprise an image capturing section 50 i, a storing section 50 s, ahorizontal transfer section 50 h, and an output section 50 d. In such asensor, the image capturing section 50 i comprises a plurality of lightreceiving pixels in a matrix arrangement and, in response to an incidentlight, stores information charges in each of the light receiving pixels.The storing section 50 s obtains information charges for one imagescreen from the image capturing section 50 i and stores the chargestherein for a predetermined period. The horizontal transfer section 50 hobtains information charges in the units of lines from the storingsection 50 s and horizontally transfers the charges in the units of onepixel. The output section 50 d converts the information charges suppliedfrom the horizontal transfer section 50 h into an image signal tooutput.

The vertical driver 64 generates a frame transfer clock φf and avertical transfer clock φV both of which have a pulse height inaccordance with the supplied, boosted voltage VOL. Specifically, a frametransfer clock φf is generated in synchronism with a verticalsynchronous signal VT, while a vertical transfer clock φV is generatedin synchronous with a vertical synchronous signal VT and a horizontalsynchronous signal HT. These clocks φf, φV are supplied to the CCD imagesensor 50.

In the CCD image sensor 50, frames are transferred in response to aframe transfer clock φf, whereby information charges stored in the imagecapturing section 50 i are collectively transferred to the storingsection 50 s at a high speed every one screen image. Further, verticaltransfer is performed in response to a vertical transfer clock φVwhereby information charges stored in the storing section 50 s arevertically transferred in the units of one horizontal line for everyperiod of a horizontal synchronous signal HT to the horizontal transfersection 50 h. Through the above operation, information charges stored inthe storing section 50 s are read out for every line and supplied to thehorizontal transfer section 50 h.

A regulating voltage VJ is also supplied to the horizontal driver 66,which in turn begins generation of a horizontal transfer clock φh and areset clock φr in synchronous with a horizontal synchronous signal HT. Ahorizontal transfer clock φh is supplied to the horizontal transfersection 50 h, so that, in response to the horizontal transfer clock φh,the information charges for one line, which have been transferred fromthe storing section 50 s and stored in the horizontal transfer section50 h, are horizontally transferred in the units of one pixel to theoutput section 50 d. Through the above operation, information chargesfor one pixel are sequentially read out from the horizontal transfersection 50 h to the output section 50 d.

The output section 50 d alternately conducts reading of the informationcharges from the horizontal transfer section 50 h for storage in afloating diffusion layer and outputting of the information charges fromthe floating diffusion layer in response to a reset clock φr.Specifically, the potential in the floating diffusion layer changesaccording to the amount of charges stored therein, so that a voltagesignal according to the changed potential is output as an image signal Y(t) from the CCD image sensor 50.

While an image is being captured, an image signal Y(t) generated by theCCD image sensor 50 is coupled by the capacitor 52 a in the clampingcircuit 52 to be extracted to the signal line 70. The extracted imagesignal is then given predetermined signal processing in the analoguesignal processing circuit 54, the A/D converter circuit 56, and thedigital signal processing circuit 58 before being output to, forexample, a display device of the like.

The clamping circuit 52, or a circuit for clamping potential of thesignal line 70, comprises a buffer circuit 52 b, which serves as areference voltage source, and a switch element 52 c for connecting thebuffer circuit 52 b and the signal line 70. The switch element 52 c iscontrolled for its turning on/off according to a clamp pulse CP,generated by the timing control circuit 60.

The timing control circuit 60 comprises a plurality of counters, eachfor counting a reference clock CK and, in response to a reference clockCK, generates various control signals directed to the clamping circuit52, the vertical driver 64, the horizontal driver 66, the regulatecircuit 68, and other circuits, as well as an internal clock CK′, whichserves as an internal system clock for the image capturing device.Through these clocks, respective circuits are controlled so as tooperate synchronously with the CCD image sensor 50.

The timing control circuit 60 responsive to an externally suppliedstand-by mode signal ST suspends operations of the boosting circuit 62and the regulate circuit 68, whereby output of the boosted voltages VOHand VOL and a regulating voltage VJ respectively from the boostingcircuit 62 and the vertical driver 64 are suspended.

The timing control circuit 60 comprises a synchronous signal generatingsection 60 a, a counter 60 b, a clamping capability control section 60c, and a clamp pulse generating section 60 d. The synchronous signalgenerating section 60 a divides a reference clock CL by a predetermineddividing ratio to thereby generate a vertical synchronous signal VT anda horizontal synchronous signal HT.

A vertical synchronous signal VT and a horizontal synchronous signal HTare used in the counter 60 b. Specifically, the counter 60 b is resetupon the powering of the image capturing device or the device's returnfrom a stand-by mode, and begins counting a pulse of the synchronoussignals VT and HT.

Based on the counted value by the counter 60 b, the clamping capabilitycontrol section 60 c generates a clamp mode signal SC. Specifically, theclamping capability control section 60 c changes the level of a clampmode signal SC from an L (low) level to an H (high) level, when thecounted value of the counter 60 b reaches a predetermined threshold.

After the start of power supply to the image capturing device or afterthe device's awakening from a stand-by mode, the clamp pulse generatingsection 60 d begins generation of a clamp pulse CP in synchronism with ahorizontal synchronous signal HT. In this generation, the clamp pulsegenerating section 60 d sets a longer width for a clamp pulse CP while aclamp mode signal SC remains at an L level, and sets a normal width whenthe level of the clamp mode signal SC is thereafter raised to an Hlevel. Consequently, the switch element 52 c remains in an ON state fora longer period than in a normal operation during a predetermined periodbefore the level of the clamp mode signal SC is raised to an H level, sothat the clamping capability of the clamping circuit 52 is enhanced.Therefore, the potential at the signal line 70 can promptly changecloser to an output voltage V_(K) of the buffer circuit 52 b inactivation of image capturing.

FIGS. 2A to 2D are timing charts explaining clamping control to beapplied at the time of start of power supply to the device of thepresent invention. FIG. 2A shows a power source in an ON/OFF state; FIG.2B shows an internal system clock CK′; FIG. 2C shows a horizontalsynchronous signal HT; and FIG. 2D shows a clamp mode signal SC.

At time t1, when the power source is turned on, oscillation of a clockCK′ synchronously begin, as well as creation of a horizontal synchronoussignal HT. The counter 60 b is reset to 0 at time t1, as describedabove, and begins counting a pulse 100 of a horizontal synchronoussignal HT, which is caused for every horizontal scanning period (1H).

The clamping capability control section 60 c controls such that a clampmode signal SC remains at an L level while the counted value is equal toor smaller than a predetermined threshold, that is, “3” here, and ischanged to be at an H level at a time t2, at which the counted valueexceeds the threshold, becoming “4” here. That is, the clamp pulsegenerating section 60 d controls such that clamping capability of theclamping circuit 52 remains enhanced during a period between time t1 andtime t2, in which the clamp mode signal SC remains at an L level, andthat the clamping capability is reduced to remain at such a level thatenables reduction of combing noise to below an acceptable level during aperiod after time t2.

FIGS. 3A to 3C are timing charts respectively explaining a horizontalsynchronous signal HT, a clamp pulse CP, and a clamp mode signal SC.Specifically, a clamp pulse CP 30 synchronous with a horizontalsynchronous signal HT is generated. In particular, while the clampingcapability control section 60 c controls such that a clamp mode signalSC remains at an L level, the clamp pulse generating section 60 d causesa clamp pulse 30 having a pulse width (L+ΔL), that is, larger than adefault width L by an additional amount ΔL, and while the clampingcapability control section 60 c controls such that a clamp mode signalSC remains at an H level, the clamp pulse generating section 60 d causesa clamp pulse 30 having a normal width L.

As described above, a clamp pulse CP is used in on/off control of theswitch element 52 c. That is, the switch element 52 c remains in an ONstate during a period corresponding to the pulse width of a clamp pulseCP. Therefore, while a clamp mode signal SC remains at an L level, theswitch element 52 c resultantly remains in an ON state for a periodcorresponding to a pulse width (L+ΔL), during which the clamping circuit52 continues clamping the potential of the signal line 70. Meanwhile,while a clamp mode signal SC remains at an H level, the switch element52 c resultantly remains in an ON state for a period corresponding to apulse width L, during which the clamping circuit 52 continues clampingthe potential of the signal line 70.

That is, during a predetermined period after start of power supply tothe image capturing device, the clamping circuit 52 continues operatingfor a period of time which is elongated by an additional amount ΔL of apulse width. Consequently, clamping capability is enhanced. It should benoted that an additional amount ΔL may either be constant or change inthe predetermined period t after start of supply of power to the imagecapturing device.

FIG. 4 shows relationship between the time elapsed after start of powersupply to the image capturing device and the additional amount ΔL of apulse width. In the drawing, line (a) relates to a case wherein aconstant additional amount ΔL is maintained, line (b) relates to a casewherein the additional amount ΔL is maintained constant for apredetermined period and is thereafter gradually reduced until time t,and line (c) relates to a case wherein the additional amount ΔL islinearly reduced. The clamp pulse generating section 60 d employs any ofthese patterns relative to an additional amount ΔL to determine a pulsewidth (L+ΔL) of a clamp pulse CP. Patterns (a), (b), and (c) may beselected as desired or according to specific conditions.

Here, the potential of the signal line 70, to which an image signal isextracted by means of coupling by a capacitor, changes depending on aperiod of time in which the CCD image sensor 50 remains inoperativeafter suspension and before resumption of image capturing, or aninoperative period. That is, a longer inoperative period results alarger difference in potential at the signal line 70 between when theCCD image sensor 50 is operating and when it is not due to dischargefrom the capacitor 52 a. Therefore, the timing control circuit 60 maymeasure an inoperative period of time by counting an internal clock orusing an internal timer and determines a suitable additional amount ΔLfor a clamp pulse CP depending on the inoperative period of time.

FIG. 5 shows a relationship between an inoperative period of time and anadditional amount ΔL of a pulse width, in which the additional amount ΔLincreases substantially proportionally to an inoperative period of time.Specifically, for an inoperative period of time t1, an additional amountΔL is set, so that the clamp pulse generating section 60 d creates, andsupplies to the switch element 52 c, a clamp pulse CP having a width(L+ΔL1) while a clamp mode signal SC remains at an L level, and a clamppulse CP having a width L while a clamp mode signal SC remains at an Hlevel. Further, for an inoperative period of time t2, an additionalpulse ΔL2 (ΔL1<ΔL2) is set, so that the clamp pulse generating section60 d creates, and supplies to the switch element 52 c, a clamp pulse CPhaving a pulse width (L+ΔL2) while a clamp mode signal SC remains at anL level and a clamp pulse CP having a pulse width ΔL while a clamp modesignal SC remains at an H level. That is, the longer the inoperativeperiod of time, the longer the switch element 52 c remains in an ONstate during a predetermined period before the CCD image sensor 50resumes operating. Consequently, the clamping capability of the clampingcircuit 52 is enhanced.

It should be noted that, although the additional amount ΔL of a pulsewidth retains substantially proportional relationship with respect to aninoperative period of time in FIG. 5, any other function which canincrease an additional amount ΔL relative to a longer inoperative periodcan be employed.

After supply of power begins, an additional amount ΔL is maintainedconstant within a predetermined period t. Alternatively, an additionalamount ΔL may be reduced over time, or reduced or increased depending onan inoperative period. An additional amount ΔL may be determined throughany desirable combination of these conditions.

FIG. 6 shows variation of the additional amount ΔL over time subsequentto the start of power supply. As shown, an additional amount ΔL is setat an finite value during a period from time 0 to time t. When apreceding inoperative period is longer than a predetermined thresholdperiod, the additional amount ΔL is maintained at a constant value ΔL2until a predetermined period to has elapsed, and is thereafter graduallyreduced after time t0 to time t (α). Meanwhile, when a precedinginoperative period is not longer than a predetermined threshold periodof time, an additional amount ΔL is kept at a constant value ΔL1 (β).Note that the relationship ΔL1<ΔL2 is maintained in the above.

According to the pattern α, in which an additional amount ΔL is variedduring a period from time 0 to time t, and additionally according to aninoperative period of time, significantly enhanced clamping capabilitycan be obtained during a period from time 0 to time t, so that thepotential of the signal line 70 can promptly change closer to Vk.

FIGS. 7A to 7E are timing charts explaining clamping control to beapplied when the device of the present invention returns from a stand-bymode. FIG. 7A relates to a power source in an ON/OFF state, FIG. 7Brelates to a stand-by mode signal ST, FIG. 7C relates to an internalsystem clock CK′, FIG. 7D relates to a horizontal synchronous signal HT,and FIG. 7E relates to a clamp mode signal SC.

Specifically, at time t1, a stand-by mode signal ST switches from an Llevel to an H level to thereby instruct the device to awaken from astand-by mode. In synchronism with the switching, oscillation of theclock CK′ begins, as does creation of a horizontal synchronous signalHT. Similar to the time of starting of the power supply, as describedwith reference to FIG. 2, the clamping capability control section 60 ccontrols such that a clamp mode signal SC remains at an L level whilethe counted value is equal to or smaller than a predetermined threshold,which is “3” here, and i set to an H level at a time t2, at which thecounted value exceeds the threshold, becoming “4” here. That is, theclamp pulse generating section 60 d controls such that clampingcapability of the clamping circuit 52 remains enhanced during a periodbetween time t1 and time t2, in which the clamp mode signal SC remainsat an L level, and that the clamping capability is reduced to remain ata level that enables reduction of combing noise to below an acceptablelevel during a period after time t2.

While in the above structure clamping capability of the clamping circuit52 is controlled according to the width of a clamp pulse CP, whichcorresponds to a period in which the switch element 52 c remains in anON state, the clamping capability can also be controlled by increasingor decreasing an amount of current to be supplied from the clampingcircuit 52 to the signal line 70 while the switch element 52 c remainsin an ON state.

FIG. 8 schematically shows another structure of a clamping circuit.Specifically, a clamping circuit 72 for clamping an output from a CCDimage sensor 50 comprises a switch element 72 c, two buffer circuits 72b, 72 b arranged in parallel, and a selector 72 d for selecting anoutput from either the buffer circuit 72 b or 72 b′ to supply to theswitch element 72 c.

With this structure, when the buffer circuit 72 b is supplied with alarger amount of current than that supplied to the buffer circuit 72 b′,the selector 72 d selects an output from the buffer circuit 72 b duringa period from time t1 to t2, and an output from the buffer circuit 72 b′in a subsequent normal operation. In the above, a signal SC can be usedas a select signal for controlling switching of the selection by theselector 72 d. In this case, specifically, the buffer circuit 72 bselects the buffer circuit 72 b while it is supplied with a controlsignal at an L level, and the buffer circuit 72 b′ while it is suppliedwith a control signal at an H Level.

It should be noted that, with the structure of FIG. 8, in order toenhance clamping capability during a period from time t1 to time t2 ascompared to during a normal operation, the selector 72 d can select, ormake effective, both outputs from the buffer circuit 72 b and 72 b′.That is, different levels of clamping capabilities can be set throughdesirable combination of buffer circuits to be selected, or madeeffective. Note that the power supply capabilities of the two buffercircuits 72 b and 72 b′ may be either equal or different.

FIGS. 9 and 10 show additional examples of operation using two buffercircuits 72 b, 72 b′. Here, in order to increase or decrease clampingcapability of the image capturing circuit, the timing control circuit 60increases or decreases the width of a clamp pulse CP to be supplied tothe switch element 52 c of the clamping circuit 52, as shown in FIG. 1.Alternatively, the timing control circuit 60 supplies a clamp modesignal SC to the selector 72 d to therewith control selection by theselector 72 d such that the selector 72 selects either or both ofoutputs from the buffer circuit 72 b and 72 b′, as shown in FIG. 8.Therefore, it will be appreciated that controlling both of the switchelement 52 c and the selectors 72 b and 72 b′ by the timing controlcircuit 60 enables highly accurate adjustment of clamping capability.

Specifically, when the maximum clamping capability is required, forexample, during a predetermined period after start of power supplyfollowing a longer-than predetermined inoperative period, the selector72 d may be controlled so as to select, or make effective, both outputsfrom the buffer circuit 72 b, 72 b′ and, additionally, a clamp pulse CPhaving a pulse width (L+ΔL) is supplied to the switch element 72 c, asshown in FIG. 9.

Meanwhile, when enhanced, but not necessarily maximum, clampingcapability is required, the selector 72 d may be controlled so as toselect, or make effective, an output from only one of the buffer circuit72 b or 72 b′, which can increase clamping capability, and a clamp pulseCP having a pulse width L (or L+ΔL) is supplied to the switch element 72c, as shown in FIG. 10. The structure of FIG. 10 can attain higherclamping capability than that in a normal operation, though lower thanthe clamping capability attained using the structure of FIG. 9.

When the buffer circuits 72 b, 72 b′ can attain clamping capabilities ofequal levels, controlling the switch element 72 c and the selector 72 dcan achieve clamping capabilities of various levels as described below.

Mode (1)

-   pulse width: L+ΔL-   selector: buffer circuit 72 b and 72 b′ both effective-   clamping capability: very high    Mode (2)-   pulse width: L+ΔL-   selector: buffer circuit 72 b effective-   clamping capability: high    Mode (3)-   pulse width: L-   selector: buffer circuit 72 b and 72 b′ both effective-   clamping capability: high    Mode (4)-   pulse width: L-   selector: buffer circuit 72 b effective-   clamping capability: low (normal operation)

The timing control circuit 60 may apply control according to Mode (1)when an inoperative period is longer than a threshold period of time,and Mode (2) or (3) when an inoperative period is shorter than athreshold period of time. Further, the timing control circuit 60 maycontrol the width of a clamp pulse CP and switching of an effectivebuffer circuit or circuits based on a map which is defined as a functionof a clamp mode signal SC and an inoperative period.

In the above description of embodiments of the present invention, a CCDimage sensor 50 of a film transfer type is referred to. However,application of the present invention is not limited to such sensors, andthe present invention can be applied also to an image capturing deviceemploying a CCD image sensor of an interline type or a frame interlinetype.

1. An image capturing device, comprising: a solid image capturingelement; a driving circuit for driving the solid image capturing elementto obtain an image signal; a clamping circuit for clamping a referencelevel of the image signal generated by the solid image capturing elementat a predetermined level; and a control circuit for controlling clampingcapability of the clamping circuit; wherein the control circuit controlssuch that a clamping capability attained within a predetermined periodafter start of image capturing by the solid image capturing elementbecomes different from a clamping capability attained in another period;wherein the clamping circuit comprises two or more clamping circuitsections, and the control circuit controls such that a larger number ofclamping circuit sections operate within a predetermined period afterstart of image capturing by the solid image capturing element than inanother period.
 2. The device according to claim 1, wherein the clampingcircuit comprises two or more clamping circuit sections whichrespectively have clamping capabilities at different levels, and thecontrol circuit controls such that a clamping circuit section at ahigher level operates within a predetermined period after start of imagecapturing by the solid image capturing element while a clamping circuitsection at a lower level operates in another period.
 3. An imagecapturing device, comprising: a solid image capturing element; a drivingcircuit for driving the solid image capturing element to obtain an imagesignal; a clamping circuit for clamping a reference level of the imagesignal generated by the solid image capturing element at a predeterminedlevel; and a control circuit for controlling clamping capability of theclamping circuit; wherein the control circuit controls such that aclamping capability attained within a predetermined period after startof image capturing by the solid image capturing element becomesdifferent from a clamping capability attained in another period; whereinthe control circuit controls such that the clamping capability within apredetermined period after start of image capturing by the solid imagecapturing element becomes higher in level than the clamping capabilityattained in another period; wherein the clamping circuit comprises twoor more clamping circuit sections, and wherein the control circuitcontrols such that a larger number of clamping circuit sections operatelonger within a predetermined period after start of image capturing bythe solid image capturing element than in another period.
 4. An imagecapturing device, comprising: a solid image capturing element; a drivingcircuit for driving the solid image capturing element to obtain an imagesignal; a clamping circuit for clamping a reference level of the imagesignal generated by the solid image capturing element at a predeterminedlevel; and a control circuit for controlling clamping capability of theclamping circuit; wherein the control circuit controls such that aclamping capability attained within a predetermined period after startof image capturing by the solid image capturing element becomesdifferent from a clamping capability attained in another period; whereinthe control circuit controls such that the clamping capability within apredetermined period after start of image capturing by the solid imagecapturing element becomes higher in level than the clamping capabilityattained in another period; wherein the clamping circuit comprises twoor more clamping circuit sections which respectively have clampingcapabilities at different levels, and wherein the control circuitcontrols such that a clamping circuit section at a higher level operateslonger within a predetermined period after start of image capturing bythe solid image capturing element than in another period.
 5. An imagecapturing device, comprising: a solid image capturing element; a drivingcircuit for driving the solid image capturing element to obtain an imagesignal; a clamping circuit for clamping a reference level of the imagesignal generated by the solid image capturing element at a predeterminedlevel; and a control circuit for controlling clamping capability of theclamping circuit; wherein the control circuit controls such that aclamping capability attained within a predetermined period after startof image capturing by the solid image capturing element becomesdifferent from a clamping capability attained in another period; whereinthe control circuit controls such that the clamping circuit operateslonger within a predetermined period after start of image capturing bythe solid image capturing element than in another period; and whereinthe control circuit controls such that a clamping circuit sectionoperates, within a predetermined period after image capturing by thesolid image capturing element is started, in a period which is longer byan amount ΔL than a period L in which the clamping circuit sectionoperates in another period.
 6. An image capturing device, comprising: asolid image capturing element; a driving circuit for driving the solidimage capturing element to obtain an image signal; a clamping circuitfor clamping a reference level of the image signal generated by thesolid image capturing element at a predetermined level; and a controlcircuit for controlling clamping capability of the clamping circuit;wherein the control circuit controls such that a clamping capabilityattained within a predetermined period after start of image capturing bythe solid image capturing element becomes different from a clampingcapability attained in another period; wherein the control circuitcontrols such that the clamping circuit operates longer within apredetermined period after start of image capturing by the solid imagecapturing element than in another period; wherein the control circuitcontrols such that a clamping circuit section operates, within apredetermined period after image capturing by the solid image capturingelement is started, in a period which is longer by an amount ΔL than aperiod L in which the clamping circuit section operates in anotherperiod; and wherein the control circuit controls such that the amount ΔLremains constant within a predetermined period after commencement ofimage capturing by the solid image capturing element.
 7. An imagecapturing device, comprising: a solid image capturing element; a drivingcircuit for driving the solid image capturing element to obtain an imagesignal; a clamping circuit for clamping a reference level of the imagesignal generated by the solid image capturing element at a predeterminedlevel; and a control circuit for controlling clamping capability of theclamping circuit; wherein the control circuit controls such that aclamping capability attained within a predetermined period after startof image capturing by the solid image capturing element becomesdifferent from a clamping capability attained in another period; whereinthe control circuit controls such that the clamping circuit operateslonger within a predetermined period after start of image capturing bythe solid image capturing element than in another period; wherein thecontrol circuit controls such that a clamping circuit section operates,within a predetermined period after image capturing by the solid imagecapturing element is started, in a period which is longer by an amountΔL than a period L in which the clamping circuit section operates inanother period; and wherein the control circuit controls so as to reducethe amount ΔL within a predetermined period after commencement of imagecapturing by the solid image capturing element.
 8. An image capturingdevice, comprising: a solid image capturing element; a driving circuitfor driving the solid image capturing element to obtain an image signal;a clamping circuit for clamping a reference level of the image signalgenerated by the solid image capturing element at a predetermined level;a control circuit for controlling such that a clamping capabilityattained within a predetermined period after start of image capturing bythe solid image capturing element becomes different from a clampingcapability attained in another period; and a detection circuit formeasuring an inoperative period during which the solid image capturingelement suspends image capturing, wherein the control circuit controlssuch that the clamping capability within a predetermined period afterstart of image capturing by the solid image capturing element becomeshigher in level than the clamping capability attained in another period,and controls such that the clamping capability becomes higher in levelwith respect to a longer inoperative period.
 9. The device according toclaim 8, wherein the control circuit controls such that the clampingcircuit operates longer within a predetermined period after start ofimage capturing by the solid image capturing element than in anotherperiod, and controls such that the clamping circuits operates longerwith respect to a longer inoperative period.
 10. The device according toclaim 8, wherein the clamping circuit comprises two or more clampingcircuit sections, and the control circuit controls such that a largernumber of clamping circuit sections operate within a predeterminedperiod after start of image capturing by the solid image capturingelement than in another period, and controls such that a larger numberof clamping circuit sections operate with respect to a longerinoperative period.
 11. The device according to claim 8, wherein theclamping circuit comprises two or more clamping circuit sections havingdifferent levels of clamping capability, and the control circuitcontrols such that a clamping circuit section at a higher level operateswithin a predetermined period after start of image capturing by thesolid image capturing element while a clamping circuit section at alower level operates in another period, and controls such that theclamping capability becomes higher in level with respect to a longerinoperative period.
 12. An image capturing device, comprising: a solidimage capturing element; a driving circuit for driving the solid imagecapturing element to obtain an image signal; a clamping circuit forclamping a reference level of the image signal generated by the solidimage capturing element at a predetermined level; and a control circuitfor controlling clamping capability of the clamping circuit; wherein thecontrol circuit controls such that a clamping capability attained withina predetermined period after start of image capturing by the solid imagecapturing element becomes different from a clamping capability attainedin another period; wherein the control circuit controls such that theclamping capability within a predetermined period after start of imagecapturing by the solid image capturing element becomes higher in levelthan the clamping capability attained in another period; and furthercomprising: a buffer circuit for outputting a predetermined referencevoltage; and a switch connected between the buffer circuit and a signalline connected to an output terminal of the sold image capturingelement, for switching between in an on state and in an off state, andwherein the control circuit controls the clamping capability by changinga period in which the switch remains in an on state.
 13. An imagecapturing device, comprising: a solid image capturing element; a drivingcircuit for driving the solid image capturing element to obtain an imagesignal; a clamping circuit for clamping a reference level of the imagesignal generated by the solid image capturing element at a predeterminedlevel; and a control circuit for controlling clamping capability of theclamping circuit; wherein the control circuit controls such that aclamping capability attained within a predetermined period after startof image capturing by the solid image capturing element becomesdifferent from a clamping capability attained in another period; andfurther comprising: a plurality of buffer circuits for outputting apredetermined reference voltage; a selector for selecting at least oneof the plurality of buffer circuits; a switch connected between thebuffer circuit selected by the selector and a signal line connected toan output terminal of the solid image capturing element, for switchingbetween in an on state and in an off state, wherein the control circuitscontrols the clamping capability by changing either a type or a numberof the buffer circuit selected by the selector.
 14. An image capturingdevice, comprising: a solid image capturing element; a driving circuitfor driving the solid image capturing element to obtain an image signal;a clamping circuit for clamping a reference level of the image signalgenerated by the solid image capturing element at a predetermined level;and a control circuit for controlling clamping capability of theclamping circuit; wherein the control circuit controls such that aclamping capability attained within a predetermined period after startof image capturing by the solid image capturing element becomesdifferent from a clamping capability attained in another period; andfurther comprising: a plurality of buffer circuits for outputting apredetermined reference voltage; a selector for selecting at least oneof the plurality of buffer circuits; a switch connected between thebuffer circuit selected by the selector and a signal line connected toan output terminal of the solid image capturing element, for switchingbetween in an on state and in an off state, wherein the control circuitscontrols the clamping capability by changing at least one of a period inwhich the switch remains in an on state, a type of the buffer circuitselected by the selector, and a number of the buffer circuit selected bythe selector.